The packaging of integrated circuit (IC) chips is one of the most important steps in the manufacturing process, contributing significantly to the overall cost, performance and reliability of the packaged chip. As semiconductor devices reach higher levels of integration, packaging technologies have become critical. Packaging of the IC chip accounts for a considerable portion of the cost of producing the device and failure of the package leads to costly yield reduction.
As semiconductor device sizes have decreased, the density of devices on a chip has increased, along with the size of the chip, thereby making chip bonding more challenging. Many chip bonding technologies use solder bumps attached to a contact pad, or the bonding pad, on the chip to make a connection from the chip to the package substrate. Small solder balls are used to make many connections to package substrates when a chip is inverted and attached onto a package substrate via the solder balls. Since the solder balls can form an area array (a “ball grid array” (BGA)), this method can achieve a very high-density scheme for chip interconnections. The flip-chip method has the advantage of achieving a very high density of interconnection to the device with a very low parasitic inductance. Increasingly, the chip substrate is thinned before packaging to reduce the final size of the device and to reduce thermal expansion coefficient mismatch issues. After the solder balls are formed, a backside of the substrate is grinded to a small thickness before bonding to the package substrate.
To maintain robust electrical performance during the life of the chip package, the solder balls not only need to make a good electrical connection to the package substrate, but also need to maintain structural integrity and good electrical connection over the life of the device. Unwanted particles and residues from packaging processes can adversely affect the device performance by causing cracks in the soldered connection or increasing electrical resistance. Moreover, it is desirable to have process conditions that can accommodate a wide variety of chip designs in semiconductor manufacturing. Accordingly, there is a need for packaging methods to form residue-free bump areas after wafer grinding that allow a wide process window.